The invention relates to a configuration and a method for increasing the retention time and the storage security in a memory such as a ferroelectric memory or a ferromagnetic memory.
The retention time and the storage security of a ferroelectric or ferromagnetic semiconductor memory realized in a memory chip are critical parameters for a large number of applications of the semiconductor memories. This is because the retention time and ultimately also the storage security are determined, in all technologies used hitherto, by the xe2x80x9cinadequacyxe2x80x9d of the material respectively used. A DRAM (dynamic RAM) is used as an example for this problem; in a DRAM, the limiting factor for the retention time is given by the loss of charge of the storage capacitor on account of various material-dependent leakage mechanisms. In order to compensate for this loss of charge, refresh cycles are required in DRAMs.
In DRAMs this loss of charge is so great that they are referred to as volatile semiconductor memories. Without the refresh cycles, the retention time in DRAMs would be insufficient for practical applications.
However, also in so-called nonvolatile semiconductor memories, such as the ferroelectric semiconductor memories (FeRAMs) and the ferromagnetic semiconductor memories (MRAMs), the retention time plays a part that should not be underestimated. This is because, in FeRAMs and MRAMs, too, losses of polarization (FeRAM) or magnetization (MRAM) can be observed over relatively long periods of time.
Ferroelectric and ferromagnetic materials have the property that their hysteresis loop, in which the dependence of the polarization and magnetization, respectively, on the electric and magnetic field, respectively, is plotted, shifts in the event of frequently repeated iteration depending on the direction of the applied electric and magnetic field, respectively. This is an effect intrinsic to the ferroelectric and ferromagnetic materials (imprint effect).
It is accordingly an object of the invention to provide a configuration and a method for increasing the retention time and the storage security in a ferroelectric or ferromagnetic semiconductor memory in which the retention time and the storage security can be considerably increased through the use of simple measures.
With the foregoing and other objects in view there is provided, in accordance with the invention, a configuration for increasing a storage retention time and a storage security, including:
a memory cell array having a cell array content, the memory cell array including a plurality of memory cells including a material having a hysteresis property, the memory cells having respective cell contents and being provided in rows and columns;
a row decoder and a column decoder connected to the memory cell array for writing to the memory cells;
an evaluation unit connected to the memory cell array, the evaluation unit being configured to evaluate the cell contents of the memory cells;
a write-back register operatively connected to the evaluation unit, the write-back register being configured such that at least part of the cell array content can be written back N times into the write-back register, N being a number at least equal to one; and
a write-back controller connected to the write-back register, the write-back controller controlling a rewriting of the at least part of the cell array content, which has been written back to the write-back register, to the memory cell array via the row decoder and the column decoder.
The configuration according to the invention and the method according to the invention advantageously utilize the abovementioned intrinsic effects of the ferroelectric and ferromagnetic materials. Since, as a result of a frequently repeated iteration of the respective hysteresis loop, the latter shifts depending on the direction of the applied electric or magnetic field, it is possible in this way to increase the remanent polarization or the remanent magnetization, respectively, i.e. the magnitude of the stored digital signal, and hence the retention time as well. By way of example, if a positive electric field is frequently applied to a ferroelectric material, then its hysteresis loop shifts in the direction of this electric field, as a result of which the negative remanent polarization increases on account of the intrinsic effect, which means that the retention time is increased.
The configuration according to the invention can readily be integrated into the memory chips of FeRAMs or MRAMs. The application of the invention is particularly advantageous when a memory chip with a FeRAM or MRAM that has to comply with a high retention time or storage security, which is applicable for example when the memory chips are used in cards for access control or the memory chips generally contain personal information.
The configuration according to the invention or the method according to the invention thus makes it possible to combine the advantages of fast writing, a low voltage used, and high rewriteability of FeRAMs or MRAMs with a long retention time and hence storage security of a flash memory.
The configuration according to the invention is constructed relatively simply since it essentially requires only a write-back register and a write-back controller. The content of memory cells of a memory cell array is written back to the write-back register N times (Nxe2x89xa71). In this case, Nxe2x89xa71 preferably holds true, where N may be, for example, between 100 and 1000 or, alternatively, greater than 1000. The write-back controller allows the content of memory cells of the memory cell array that has been written back to the write-back register to be rewritten to the memory cell array via the row decoder and column decoder present anyway.
According to another feature of the invention, a write-back counter is connected to the write-back controller, the write-back counter counts the number N corresponding to a number of times the at least part of the cell array content has been written back to the write-back register.
According to yet another feature of the invention, a start/stop address buffer is connected to the write-back controller, the start/stop address buffer defines a given area in the memory cell array to be written back N times to the write-back register.
According to another feature of the invention, a write-back counter buffer is connected to the write-back counter for inputting the number N corresponding to a number of times the at least part of the cell array content is to be written back to the write-back register.
According to another feature of the invention, the memory cells are ferromagnetic memory cells or ferroelectric memory cells.
With the objects of the invention in view there is also provided, a method for increasing a retention time and a storage security in a semiconductor memory, the method includes the steps of:
providing a memory cell array including a plurality of memory cells including a material having a hysteresis property; and increasing a remanent polarization or a remanent magnetization by N times performing the operations of writing a memory content of given ones of the memory cells to the semiconductor memory, evaluating, buffer-storing, and rewriting the memory content into the given ones of the memory cells, with N being a number at least equal to one.
The method according to the invention can be performed with only a few method steps.
Firstly, the information to be stored is written to a memory cell array. Afterwards, a special write-back mode is initiated, in which it is defined how often the respective data of the individual memory cells is to be written back, which can be done for example N times (Nxe2x89xa71). Through the use of the write-back controller, each memory cell is then read out to the write-back register, its content is evaluated and the same memory cell is written to again N times after N-fold evaluations. The number N of read-out and rewriting can be set in a write-back counter. The time required for writing back can be reduced by writing to a plurality of memory cells simultaneously.
By specifying start and stop addresses of a memory cell array area to be written, it is possible to provide only a part of the respective memory chip with the configuration according to the invention, or to subject it to the method according to the invention, with the result that the polarization or magnetization and hence both the retention time and the storage security, for example relative to an elevated temperature, are increased exclusively in the part.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a configuration and a method for increasing the retention time and the storage security in a ferroelectric or ferromagnetic semiconductor memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.